FPGA 高级时序验证技术Actel

简介：高级FPGA时序验正技术

问：在进行FPGA设计时,如何避免时序的冲突问题?
如何更加有效地使用D触发器进行时序设计?
答： Basically, if you can follow synchronous design methodology, most of the timing conficts can be avoided. We plan to have another online seminar very soon, that will address the synchronous design methodology.

问：既然FPGA的时间延迟那么不确定，那么我们如何保证功能的可靠呢？
答： No, the timing delay in FPGA is certain, in the sense that it falls into a bounded range (min, typical and max). If we should design around this boundary, the reliability is not a problem. That"s why timing verification is so important

问：在IC 设计过程中用Timemill 模拟的结果可以在FPGA 时序验证是完整的
反映吗?
答： Yes, but you need to get the timing library/model for that FPGA first.

问：对于贵公司的FPGA，请推荐比较好的设计流程工具（包括功能仿真，综合，布局布线，后仿真等流程）
答： If this is a pure synchronous design, do the functional simulation with ModelSim first, then run the logic synthesis (Synplify/Exemplar), and P&R (Designer). Finally do static timing analysis (Timer).

If it is a asynchronous design, do the fun

问：寄存器是单元电路。对它的时延有何要求？请具体以数值说明。另外，它在时序验证中所起的作用，请介绍一下。
答： The most important timing requirement for FF is setup time, hold time, recovery time, removal time, clock to out delay.

The details of these requirements have been covered in this presentation.

问：如何实现FPGA和CPU之间的异步数据传输？
答： There are couple of way to do that, the most popular method is to use handshake protocol.

问： 请问若系统除主时钟以外还有一时钟是主时钟的180度相移，而且也驱动一些寄存器，那么仍属于同步设计吧？但是需要注意些什么吗
答： As long as the same clock net is used, than it is still a synchronous design. Some time (especially in ASIC design), we used anti-phasse (180% phase shifted clock) to acheive even higher timing quality design!

问：试问如果设计一个24bit的dsp core在贵公司的fpga的2000万门产品之内，最快可以达到多少速度的系统时钟，——？？——MHZ的主频，影响数度的瓶颈在哪里，谢谢。
答： It depends on the DSP core"s architecture, as multiply-and-add is the major part of most DPS, and it will become the critical path of the design. Depending on the archtecture of the MAC, the performance can vary a lot! In general, pipelined MAC can ha

问：synplify 对actel 系列芯片优化的怎样？
答： Synplify is very efficient in optimizing our FPGA, and the synthesis speed is very fast. That"s we include it in our developement package (Libero).

问：您好：
   有没有关于高级时序验证技术方面更具体的资料，如何联系。谢谢！
答： We have a application note about static timing analysis, that will be available on our website"s application note category very soon, please check it out later.